The present invention relates to a data transmitter and a data receiver, and a data transfer device which is comprised of their combination.
Recently, there have been proposed various computer systems which have multiprocessor structures with the limitations of the high-speed of computers having single processor structures. Referring to a multiprocessor system, data communication is executed between processors.
FIG. 14 is a block diagram showing the structure of a multiprocessor system according to the prior art. Referring to the multiprocessor system shown in FIG. 14, N processor elements 600 (1) to (N) are linked to one another through an interconnection network 700. The processor element 600 comprises a processor 602 for executing instructions, a memory 604 for storing instructions and data, an internal bus 606, and a data transfer device 608 for data communication with other processor elements. The data transfer device 608 includes an address generating circuit 610, an ECC circuit 612, a data latch 614 and a synchronous processing circuit 616. The address generating circuit 610 has a function of sending to the internal bus 606 addresses for sequentially fetching from the memory 604 data to be transmitted and sequentially storing received data in the memory 604. The ECC circuit 612 has an error correcting code adding circuit 650, an error checking and correction circuit 652 and an error detecting signal output circuit 654 as shown in FIG. 15, and has functions of adding error correcting codes to transmitted data and of checking and correcting the errors of received data. The data latch 614 is a circuit for temporarily holding the transmitted and received data. The synchronous processing circuit 616 serves to synchronize data communication. External buses 618 (1) to (N) are provided between the interconnection network 700 and the data latches 614 of the processor elements 600 (1) to (N). By way of example, the interconnection network 700 has a cross bar net structure as disclosed in "Theory of Parallel Computer Structure" written by Shinji Tomira, Shokodo, 1986, pp 69-99.
FIG. 16 is a time chart showing the operation of the data transfer device 608. There will be described the case where a first processor element 600 (1) and an Nth processor element 600 (N) are linked to each other through the interconnection network 700 and data is transferred from the former to the latter.
In the processor unit 600 (1) as a data source, an address (for example, ADDRESS n) of data to be transmitted is first provided from the address generating circuit 610 to the memory 604 under the control of the synchronous processing circuit 616. Data (DATA n) fetched from the memory 604 based on the address is provided to the ECC circuit 612 through a first bidirectional bus 20. In the ECC circuit 612, an error correcting code is added to the data. Then, the data is transmitted through a second bidirectional bus 22, the data latch 614 and the external bus 618 (1).
In the processor element 600 (N) as a data sink, data received through the external bus 618 (N) is first latched as received data in the data latch 614. The received data having an error correcting code which is latched in the data latch 614 is provided to the error checking and correction circuit 652 of the ECC circuit 612 through the second bidirectional bus 22 and is then checked. In the case where the received data has no errors, the error checking and correction circuit 652 outputs the received data itself to the first bidirectional bus 20. In the case where the errors of the received data can be corrected, data obtained by correcting the received data is outputted to the first bidirectional bus 20. The received data is stored in the memory 604 through the internal bus 606. The storage location in the memory 604 is specified by the address generating circuit 610. In the case where the error checking and correction circuit 652 detects that the received data has errors which cannot be corrected, it generates an error detecting signal 24 through the output circuit 654. The synchronous processing circuit 616 sends to the external bus 618 (N) a response corresponding to the generation of the error detecting signal 24.
In the processor unit 600 (1) as the data source, the response from the processor element 600 (N) is received by the data latch 614 through the external bus 618 (1) and is then received by the synchronous processing circuit 616. As the result of decision on the response, if it is confirmed that the previously transmitted data (for example, DATA n) is correctly received by the data sink, the synchronous processing circuit 616 causes the address generating circuit 610 to generate the next address (ADDRESS n+1) and to transmit the next data (DATA n+1). In the case where the synchronous processing circuit 616 receives a response (retransmission request) which indicates that the transmitted data (for example, DATA n+1) is not correctly received by the data sink, it causes the address generating circuit 610 to stop the generation of the next address (ADDRESS n+2) and to transmit the same data as retransmission data (RDATA n+1).
Referring to the data transfer device 608 according to the prior art, if it is confirmed that the transferred data is correctly received by the data sink, the next data is transmitted. Consequently, a data transfer speed is low. Therefore, the processing efficiency of the entire multiprocessor system is remarkably lowered.
It is an object of the present invention to realize high-speed data transfer and smooth data retransmission.